1. Technical Field
The present invention relates to the field of computer systems, and in particular to devices for analyzing the performance of computer systems.
2. Background Art
Modern computer systems are typically configured as multiple resources that communicate through a bus system. These resources may include a central processing unit (processor), memory, graphics system, and I/O devices. In many instances, system logic is coupled to the bus system to regulate transactions among the resources. Real-time observations of these transactions provide useful information about the system's efficiency and potential bottlenecks in data flow among system resources. This information includes, for example, the average number of instructions in a resource queue, the latency of a request operation, and the frequency with which transactions between one pair of resources are stalled by transactions between another pair of resources. This information may be used by both hardware and software designers to improve system performance.
In many instances, understanding performance bottlenecks requires relatively complex operations. For example, pinpointing pathological operations may require detecting concurrent transactions between different pairs of resources. Collisions between these concurrent transactions can indicate device or instruction interactions that are not apparent when monitoring either event separately. Latency experiments must track the time difference between the arrival of a request signal and the completion of the requested action. Where multiple resources share a transaction queue, it may be difficult to disentangle signals for the different resources, and complex analyses of available signals may be required to obtain the desired information.
Currently available methods for monitoring events in computer systems are limited by the types of signals that can be observed and the ease with which observations can be made. Logic analyzers are general purpose devices that can be set up to monitor the state of selected external signal lines when a specified instruction is detected. Here, "external signals" refers to those signals that are transferred on a bus or other readily accessible signal line. Events represented by signals internal to chip or system are not available for analysis by logic analyzers, and more sophisticated operations, such as detecting concurrent events involving non-external signals, are precluded with logic analyzers. These devices are also relatively expensive and complex to operate, limiting their use to engineers who design and debug the hardware.
Various programmable logic devices (PLDs) can also be used to monitor the operation of system hardware. These are usually designed for specific hardware devices and are complex to use. In addition, PLDs, like logic analyzers only have access to external signals.
There is thus a need for a transparent system capable of monitoring computer systems at a sufficiently detailed level to provide meaningful feedback on resource performance without need for complex interfacing and analysis procedures.